`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:39:58 06/23/2014 
// Design Name: 
// Module Name:    addr_mapping 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module addr_mapping 
#(
   parameter integer C_SIPIF_DWIDTH       = 32,
   parameter integer C_SPLB_AWIDTH        = 32,
   parameter integer C_SPLB_DWIDTH        = 32,
	parameter integer C_BURST_LEN_WIDTH		= 7,
	parameter integer C_CS_WIDTH				= 1,
	parameter integer C_RDCE_WIDTH			= 1,
	parameter integer C_WRCE_WIDTH			= 1

   //parameter integer C_ARD_ADDR_RANGE_ARRAY        = 1,
   //parameter integer C_ARD_NUM_CE_ARRAY = 1
)
(
        //-- IP Interconnect (IPIC) port signals -----------------------------------------
        
        //-- left side -------------------------------------------------------------
        input Bus2IP_Clk_l, 
        input Bus2IP_Reset_l,
        
        output [0 : C_SIPIF_DWIDTH-1] IP2Bus_Data_l,
        output IP2Bus_WrAck_l,
        output IP2Bus_RdAck_l,
        output IP2Bus_AddrAck_l,
        output IP2Bus_Error_l,
        
        input [0 : C_SPLB_AWIDTH-1] Bus2IP_Addr_l,
        input [0 : C_SIPIF_DWIDTH-1] Bus2IP_Data_l,
        input Bus2IP_RNW_l,
        input [0 : (C_SIPIF_DWIDTH/8)-1] Bus2IP_BE_l,
        input Bus2IP_Burst_l,
        input [0 : C_BURST_LEN_WIDTH - 1] Bus2IP_BurstLength_l, // [0 : log2(16 * (C_SPLB_DWIDTH/8))] Bus2IP_BurstLength_l,
        input Bus2IP_WrReq_l,
        input Bus2IP_RdReq_l,
        //input [0 : ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1] Bus2IP_CS_l,
        //input [0 : calc_num_ce(C_ARD_NUM_CE_ARRAY)-1] Bus2IP_RdCE_l,
        //input [0 : calc_num_ce(C_ARD_NUM_CE_ARRAY)-1] Bus2IP_WrCE_l,
		  input [0 : C_CS_WIDTH - 1] Bus2IP_CS_l,
        input [0 : C_RDCE_WIDTH - 1] Bus2IP_RdCE_l,
        input [0 : C_WRCE_WIDTH - 1] Bus2IP_WrCE_l,
        
        //-- right side -------------------------------------------------------------
        output Bus2IP_Clk, 
        output Bus2IP_Reset,
        input [0 : C_SIPIF_DWIDTH-1] IP2Bus_Data,
        input IP2Bus_WrAck,
        input IP2Bus_RdAck,
        input IP2Bus_AddrAck,
        input IP2Bus_Error,
        output [0 : C_SPLB_AWIDTH-1] Bus2IP_Addr,
        output [0 : C_SIPIF_DWIDTH-1] Bus2IP_Data,
        output Bus2IP_RNW,
        output [0 : (C_SIPIF_DWIDTH/8)-1] Bus2IP_BE,
        output Bus2IP_Burst,
        output [0 : C_BURST_LEN_WIDTH - 1] Bus2IP_BurstLength, //[0 : log2(16 * (C_SPLB_DWIDTH/8))] Bus2IP_BurstLength,
        output Bus2IP_WrReq,
        output Bus2IP_RdReq,
        //output [0 : ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1] Bus2IP_CS,
        //output [0 : calc_num_ce(C_ARD_NUM_CE_ARRAY)-1] Bus2IP_RdCE,
        //output [0 : calc_num_ce(C_ARD_NUM_CE_ARRAY)-1] Bus2IP_WrCE
		  output [0 : C_CS_WIDTH - 1] Bus2IP_CS,
        output [0 : C_RDCE_WIDTH - 1] Bus2IP_RdCE,
        output [0 : C_WRCE_WIDTH - 1] Bus2IP_WrCE
                                    
    );
    
	 wire clk = Bus2IP_Clk_l;
	 wire rst = Bus2IP_Reset_l;
	 
	 wire [C_SPLB_AWIDTH-1 : 0] addr = Bus2IP_Addr_l;
	 wire [1:0] addr_offset;
	 wire [9:0] addr_col;
	 wire [5:0] addr_row;
	 wire [1:0] addr_bank;
	 
	 assign addr_offset = addr[1:0];
	 assign addr_col = addr[11:2];
	 assign addr_row = addr[17:12];
	 assign addr_bank = addr[19:18];
	 
	 wire [9:0] mapped_addr_col;
	 wire [5:0] mapped_addr_row;
	 wire [1:0] mapped_addr_bank;
	 wire [19:0] mapped_addr;
	 
	 wire [5:0] s_blk_offset; //offset in the super block
	 wire [3:0] s_blk_num; // index of the super block
	 wire [11:0] addr_super_block;
	 
	 wire [3:0] addr_v; // BCRM mapping, column address
	 wire [7:0] addr_u; // BCRM mapping, row address
	 
	 assign s_blk_offset = addr[7:2];
	 assign addr_super_block = addr[19:8];
	 
	 /****** BCRM mapping  *********************/
	 // addr_v = addr_super_block % 11
	 mod_11_12bit mod_11_entity (
		.in (addr_super_block),
		.out (addr_v)
	 );
	 
	 // addr_u = (addr_super_block - addr_v) % rows
	 assign addr_u = (addr_super_block - addr_v) % (1 << 8);
	 // mapped_addr_col = s_blk_idx * 16 * (4 + 1) + s_blk_offset + s_blk_offset / 4;
	 wire [9:0] temp;
	 wire [3:0] sub_blk_num; // the block number in a super block
	 assign temp = addr_v << 4;
	 assign sub_blk_num = s_blk_offset >> 2;
	 assign mapped_addr_col = (temp << 2) + temp + s_blk_offset + sub_blk_num;
	 assign mapped_addr = {addr_u, mapped_addr_col, addr_offset};
	 
	 /***** 1 request to 2 requests State Machine *************************/
	 reg [3:0] CUR_STATE, NEX_STATE;
	 parameter [3:0] 
	 IDLE = 0,
	 RD_S1_WAITING = 1,
	 RD_S1_FINISHED = 2,
	 RD_S2_WAITING = 3,
	 RD_S2_FINISHED = 4,
	 WR_S1_WAITING = 5,
	 WR_S1_FINISHED = 6,
	 WR_S2_WAITING = 7,
	 WR_S2_FINISHED = 8,
	 WR_S3_WAITING = 9,
	 WR_S3_FINISHED = 10,
	 
	 DELAY_S1 = 11,
	 DELAY_S2 = 12,
	 DELAY_S3 = 13,
	 DELAY_S4 = 14,
	 DELAY_S5 = 15;

	 reg [C_SPLB_AWIDTH-1 : 0] reg_mapped_addr;
	 reg [(C_SIPIF_DWIDTH/8)-1 : 0] reg_bus2ip_be;
	 reg reg_bus2ip_rnw;
	 reg reg_bus2ip_cs;
	 reg reg_bus2ip_rdce;
	 reg reg_bus2ip_wrce;
	 reg [C_SIPIF_DWIDTH-1 : 0] reg_bus2ip_data;
	 
	 reg [C_SIPIF_DWIDTH-1 : 0] reg_ip2bus_data;
	 reg reg_ip2bus_wrack;
	 reg reg_ip2bus_rdack;
	 reg reg_ip2bus_err;
	 
	 reg [C_SPLB_AWIDTH-1 : 0] bkped_addr;
	 reg [(C_SIPIF_DWIDTH/8)-1 : 0] bkped_bus2ip_be;
	 reg [C_SIPIF_DWIDTH-1 : 0] bkped_ip2bus_data;
	 
	 always @ (posedge clk) begin
		if ((Bus2IP_CS_l == 1)) begin
			bkped_addr <= mapped_addr;
		end else begin
			bkped_addr <= bkped_addr;
		end
	 end
	 
	 always @ (posedge clk) begin
		if ((IP2Bus_RdAck == 1)) begin
			bkped_ip2bus_data <= IP2Bus_Data;
		end else begin
			bkped_ip2bus_data <= bkped_ip2bus_data;
		end
	 end
	 
/******************** ECC Correction ***********************/
	wire [C_SIPIF_DWIDTH-1 : 0] ecc_corrected_data;
	wire [7:0] ecc_code_cal;
	reg [7:0] ecc_code_read;
	wire [C_SPLB_AWIDTH-1 : 0] ecc_addr;
	wire [9:0] ecc_addr_col;
	wire [1:0] sub_blk_offset;

	 // ecc_addr_col = s_blk_idx * 16 * (4 + 1) + (sub_blk_num * 5 + 4);
	 // sub_blk_offset is used to select which ecc byte is used for current data
	 assign sub_blk_offset = s_blk_offset % 4;
	 assign ecc_addr_col = (temp << 2) + temp + ((sub_blk_num << 2) + sub_blk_num + 4);
	 assign ecc_addr = {addr_u, ecc_addr_col, addr_offset};

	ecc_cal entity_ecc_cal(
      .data(bkped_ip2bus_data), 
		.ecc_code(ecc_code_cal)                            
	);
	
	 ecc_correction entity_ecc_correction (
		//.data(bkped_ip2bus_data ^ 32'h00000001),
		.data(bkped_ip2bus_data),
		.ecc_code(ecc_code_read),
		.data_corrected(ecc_corrected_data)
	 );
	 
	 always @ * begin
			case (sub_blk_offset)
				4'b00: ecc_code_read <= IP2Bus_Data[24:31];
				4'b01: ecc_code_read <= IP2Bus_Data[16:23];
				4'b10: ecc_code_read <= IP2Bus_Data[8:15];
				4'b11: ecc_code_read <= IP2Bus_Data[0:7];
			endcase
	 end
	 
	 always @ (posedge clk or posedge rst) begin
			if (rst) begin
				CUR_STATE <= IDLE;
			end else begin
				CUR_STATE <= NEX_STATE;
			end
	 end
		
	 always @ * 
	 begin
		case (CUR_STATE)
			IDLE: begin
				if ((Bus2IP_CS_l == 1) && (Bus2IP_RNW_l == 1)) begin
					
					if (IP2Bus_RdAck) begin
						NEX_STATE <= RD_S1_FINISHED;
					end else begin
						NEX_STATE <= RD_S1_WAITING;
					end
					
					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= 15;
					reg_bus2ip_rnw <= 1;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 1;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
				end else if ((Bus2IP_CS_l == 1) && (Bus2IP_RNW_l == 0)) begin
				
					if (IP2Bus_WrAck) begin
						NEX_STATE <= WR_S1_FINISHED;
					end else begin
						NEX_STATE <= WR_S1_WAITING;
					end
					
					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= Bus2IP_BE_l;
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 1;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
				end else begin
					
					NEX_STATE <= IDLE;

					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= Bus2IP_BE_l;
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 0;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= 0;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
				end
			end
			
			RD_S1_WAITING: begin
			
				if (IP2Bus_RdAck == 1'b1) begin
					
					NEX_STATE <= RD_S1_FINISHED;

					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= 15;
					reg_bus2ip_rnw <= 1;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 1;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
				end else begin
					NEX_STATE <= RD_S1_WAITING;
					
					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= 15;
					reg_bus2ip_rnw <= 1;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 1;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
				end
			end
			
			RD_S1_FINISHED: begin
					
					NEX_STATE <= RD_S2_WAITING;
					
					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= 0;
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 0;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
			end
			
			RD_S2_WAITING: begin
				if (IP2Bus_RdAck == 1'b1) begin
					
					NEX_STATE <= IDLE;
					
					reg_mapped_addr <= ecc_addr;
					reg_bus2ip_be <= 15;
					reg_bus2ip_rnw <= 1;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 1;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= ecc_corrected_data;
					reg_ip2bus_rdack <= 1;
					reg_ip2bus_wrack <= IP2Bus_WrAck;
					reg_ip2bus_err <= IP2Bus_Error;
				end else begin
				
					NEX_STATE <= RD_S2_WAITING;

					reg_mapped_addr <= ecc_addr;
					reg_bus2ip_be <= 15;
					reg_bus2ip_rnw <= 1;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 1;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= IP2Bus_WrAck;
					reg_ip2bus_err <= IP2Bus_Error;
				end	

			end
			
			RD_S2_FINISHED: begin
				
				if (Bus2IP_CS_l == 1) begin
					NEX_STATE <= RD_S2_FINISHED;
				end else begin
					NEX_STATE <= IDLE;
				end

					reg_mapped_addr <= 0;
					reg_bus2ip_be <= 0;
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 0;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= 0;
					
					reg_ip2bus_data <= 0;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= IP2Bus_WrAck;
					reg_ip2bus_err <= IP2Bus_Error;
			end
					
			WR_S1_WAITING: begin

				if (IP2Bus_WrAck) begin
					NEX_STATE <= WR_S1_FINISHED;
					
						reg_mapped_addr <= mapped_addr;
						reg_bus2ip_be <= Bus2IP_BE_l;
						reg_bus2ip_rnw <= 0;
						reg_bus2ip_cs <= 1;
						reg_bus2ip_rdce <= 0;
						reg_bus2ip_wrce <= 1;
						reg_bus2ip_data <= Bus2IP_Data_l;
						
						reg_ip2bus_data <= IP2Bus_Data;
						reg_ip2bus_rdack <= 0;
						reg_ip2bus_wrack <= 0;
						reg_ip2bus_err <= IP2Bus_Error;
				end else begin
					NEX_STATE <= WR_S1_WAITING;
					
						reg_mapped_addr <= mapped_addr;
						reg_bus2ip_be <= Bus2IP_BE_l;
						reg_bus2ip_rnw <= 0;
						reg_bus2ip_cs <= 1;
						reg_bus2ip_rdce <= 0;
						reg_bus2ip_wrce <= 1;
						reg_bus2ip_data <= Bus2IP_Data_l;
						
						reg_ip2bus_data <= IP2Bus_Data;
						reg_ip2bus_rdack <= 0;
						reg_ip2bus_wrack <= 0;
						reg_ip2bus_err <= IP2Bus_Error;
				end
			end		

			WR_S1_FINISHED: begin
			
				NEX_STATE <= WR_S2_WAITING;
		
					reg_mapped_addr <= 0;
					reg_bus2ip_be <= 0;
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 0;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= 0;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
			end	

			WR_S2_WAITING: begin  // read
				
				if (IP2Bus_RdAck == 1'b1) begin
					NEX_STATE <= WR_S2_FINISHED;
				end else begin
					NEX_STATE <= WR_S2_WAITING;
				end
			
					reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= 15; // 4 bytes
					reg_bus2ip_rnw <= 1;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 1;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
			end	

			WR_S2_FINISHED: begin
				
				NEX_STATE <= WR_S3_WAITING;
				
				reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= 0;
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 0;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 0;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					reg_ip2bus_wrack <= 0;
					reg_ip2bus_err <= IP2Bus_Error;
			end	
			
			WR_S3_WAITING: begin  // write
			
				if (IP2Bus_WrAck == 1'b1) begin
					NEX_STATE <= IDLE;
					reg_ip2bus_wrack <= 1;
				end else begin
					NEX_STATE <= WR_S3_WAITING;
					reg_ip2bus_wrack <= 0;
				end
				
				reg_mapped_addr <= ecc_addr;
					
					reg_bus2ip_rnw <= 0;
					reg_bus2ip_cs <= 1;
					reg_bus2ip_rdce <= 0;
					reg_bus2ip_wrce <= 1;
					
					// write ecc code 
					case (sub_blk_offset)
						2'b00: begin 
							reg_bus2ip_data <= {8'h00, 8'h00, 8'h00, ecc_code_cal};
							reg_bus2ip_be <= 4'b0001;
						end
						2'b01: begin
							reg_bus2ip_data <= {8'h00, 8'h00, ecc_code_cal, 8'h00};
							reg_bus2ip_be <= 4'b0010;
						end
						2'b10: begin 
							reg_bus2ip_data <= {8'h00, ecc_code_cal, 8'h00, 8'h00};
							reg_bus2ip_be <= 4'b0100;
						end
						2'b11: begin 
							reg_bus2ip_data <= {ecc_code_cal, 8'h00, 8'h00, 8'h00};
							reg_bus2ip_be <= 4'b1000;
						end
					endcase
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= 0;
					
					reg_ip2bus_err <= IP2Bus_Error;
			end	
			
			WR_S3_FINISHED: begin
			
				NEX_STATE <= IDLE;
				reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= Bus2IP_BE_l;
					reg_bus2ip_rnw <= Bus2IP_RNW_l;
					reg_bus2ip_cs <= Bus2IP_CS_l;
					reg_bus2ip_rdce <= Bus2IP_RdCE_l;
					reg_bus2ip_wrce <= Bus2IP_WrCE_l;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= IP2Bus_RdAck;
					reg_ip2bus_wrack <= IP2Bus_WrAck;
					reg_ip2bus_err <= IP2Bus_Error;
			end				
					
			default: begin
				
				NEX_STATE <= IDLE;
			
				reg_mapped_addr <= mapped_addr;
					reg_bus2ip_be <= Bus2IP_BE_l;
					reg_bus2ip_rnw <= Bus2IP_RNW_l;
					reg_bus2ip_cs <= Bus2IP_CS_l;
					reg_bus2ip_rdce <= Bus2IP_RdCE_l;
					reg_bus2ip_wrce <= Bus2IP_WrCE_l;
					reg_bus2ip_data <= Bus2IP_Data_l;
					
					reg_ip2bus_data <= IP2Bus_Data;
					reg_ip2bus_rdack <= IP2Bus_RdAck;
					reg_ip2bus_wrack <= IP2Bus_WrAck;
					reg_ip2bus_err <= IP2Bus_Error;
			end
			
		endcase
	 end

        assign Bus2IP_Clk =  Bus2IP_Clk_l;
        assign Bus2IP_Reset = Bus2IP_Reset_l;
		  
        assign Bus2IP_Addr = reg_mapped_addr; //mapped_addr;
        assign Bus2IP_Data = reg_bus2ip_data; //Bus2IP_Data_l;
        assign Bus2IP_RNW = reg_bus2ip_rnw; //Bus2IP_RNW_l;
        assign Bus2IP_BE = reg_bus2ip_be;  //Bus2IP_BE_l;
		  
        assign Bus2IP_Burst = 0; //Bus2IP_Burst_l;
        assign Bus2IP_BurstLength = 0; //Bus2IP_BurstLength_l;
		  
        assign Bus2IP_WrReq = Bus2IP_WrReq_l;
        assign Bus2IP_RdReq = Bus2IP_RdReq_l;
        assign Bus2IP_CS = reg_bus2ip_cs; //Bus2IP_CS_l;
        assign Bus2IP_RdCE = reg_bus2ip_rdce; //Bus2IP_RdCE_l;
        assign Bus2IP_WrCE = reg_bus2ip_wrce; //Bus2IP_WrCE_l;
        
        assign IP2Bus_Data_l = reg_ip2bus_data; //IP2Bus_Data;
        assign IP2Bus_WrAck_l = reg_ip2bus_wrack; //IP2Bus_WrAck;
        assign IP2Bus_RdAck_l = reg_ip2bus_rdack; //IP2Bus_RdAck; 
        assign IP2Bus_AddrAck_l = IP2Bus_AddrAck; // set 0 doesn't work
        assign IP2Bus_Error_l = reg_ip2bus_err;  //IP2Bus_Error;
endmodule
